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Chapter 14: AltLab Library
14–17
Figure 14–6 shows an example with the Subsystem Builder block.
Figure 14–6. Example With the Subsystem Builder Block
TestBench
The TestBench block controls the generation of a testbench. If the ModelSim
executable ( vsim.exe ) is available on your path, you can load the testbench into
ModelSim and compare the results with Simulink. Input and output vectors are
generated when you use the Compare against HD L option in the Simple tab or Run
Simulink in the Advanced tab.
You can optionally launch the ModelSim GUI to visually view the ModelSim
simulation.
1
Enabling testbench generation may slow simulation as all input and output values are
stored to a file.
Table 14–19 shows the TestBench block parameters.
Table 14–19. TestBench Block Parameters
Name
Value
Description
Enable Testbench generation On or Off
Turn on to enable automatic testbench generation.
Compare against HDL
Generate HDL
Run Simulink
Run ModelSim
Launch GUI
Compare Results
Mark ModelSim Unknowns
(X’s) as
Maximum number of
mismatches to display
—
—
—
—
On or Off
—
Error ,
Warning,
Info
>=0
Default = 10
Click to generate HDL, run Simulink and compare the Simulink simulation
results with ModelSim.
Click to generate a VHDL testbench from the Simulink model.
Re-run the Simulink simulation.
Load the testbench into the ModelSim simulator.
Turn on to launch the ModelSim graphical user interface.
Compare the Simulink and ModelSim results.
Display ModelSim unknown values as error, warning, or info messages. Errors
display in red; warnings in blue; info in green.
Specify the maximum number of mismatches to display.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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